The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
10 Gigabit Ethernet, a popular and growing technology, is standardized in the IEEE 802.3ae Standard. For example, the IEEE 802.3ae Standard specifies a 10 Gigabit Media Independent Interface (XGMII) between a media access controller (MAC) and a physical layer device (PHY). XGMII provides a full duplex channel operating at 10 gigabits per second (Gbps). For each direction, XGMII includes 36 parallel signals: a 32-bit data path, and four control signals (one control signal per eight bits of data). A total signal width of XGMII (including two clock signals) is 74 signals. Because of the width of XGMII, chip-to-chip, board-to-board, and other interfacing using XGMII is impractical (e.g., due to large pin counts, etc.). A physical coding sublayer (PCS) can be used with a serializer/deserializer (SERDES) to reduce the signal width to a more manageable number while maintaining data rate. For example, a 10GBASE-R PCS, which is compliant with Clause 49 of the IEEE 802.3ae Standard, can be used with a one-lane SERDES to reduce the signal width to only one signal (e.g., one differential signal) in each direction. However, the 10GBASE-R PCS is associated with various limitations restricting how XGMII signals can be encoded. Moreover, XGMII itself is associated with various coding limitations.